1. Field of the Invention
The present invention relates generally to host adapters, and more particularly, I/O bus interface circuits, either host adapters or targets, on an I/O bus, that include a plurality of bus masters for an internal communication bus.
2. Description of Related Art
Prior single chip host adapters have included a plurality of modules and an on-chip processor that controlled operation of the modules. For example, U.S. Pat. No. 5,659,690, entitled "Programmably Configurable Host Adapter Integrated Circuit Including a RISC Processor," issued on Aug. 19, 1997 to Stuber et al., which is incorporated herein by reference, had an internal bus that coupled the various modules to a sequencer that included a RISC processor.
Specifically, a SCSI module 130, a sequencer 120, data FIFO memory circuit 160, a memory 140, and a host interface module 110 were interconnected by an internal chip I/O bus CIOBUS, which was used for control of host adapter integrated circuit 100 both by a host microprocessor 170 through a host adapter driver 165 and by sequencer 120. Internal chip I/O bus CIOBUS included (i) a source bus with separate eight bit address and data buses, (ii) a destination bus with separate eight bit address and data buses, and (iii) a plurality of control signal lines. Internal chip I/O bus CIOBUS supported high speed normal operations that were controlled by sequencer 120 as well as slower but extended operations during error recovery that were controlled by host adapter driver 165 using host microprocessor 165.
The splitting of internal chip I/O bus CIOBUS into source and destination buses allowed each sequencer instruction to be completed in a single sequencer clock cycle, as opposed to the multiple cycles needed on a shared bus. Further, in some cases, a write operation and a read operation were performed simultaneously over internal chip I/O bus CIOBUS.
Both host adapter driver 165 and sequencer 120 were bus masters of bus CIOBUS. To prevent contentions on bus CIOBUS, when host adapter driver 165 wanted control of bus CIOBUS, host adapter driver 165 set a bit PAUSE in host adapter 100. When bit PAUSE was set, sequencer 120 paused and set a bit PAUSEACK. Upon setting of bit PAUSEACK, control of bus CIOBUS was transferred from sequencer 120 to host adapter driver 165 so that host adapter driver 165 could access any register in the address space of bus CIOBUS. Host adapter driver 165 polled bit PAUSEACK to determine when bus CIOBUS was available.
Thus, bus CIOBUS was operated in two modes defined by the state of bit PAUSEACK. When bit PAUSEACK was in the inactive state, bus CIOBUS supported both a write operation and a read operation within a single sequencer clock cycle, and was controlled by sequencer 120. When bit PAUSEACK was in the active state, the I/O system board or any other bus master through host interface module 110 could access any registers in host module 110 as well as any registers in host adapter 100 that were on bus CIOBUS.
Sequencer 120 could be paused at any time during normal operation. However, this could result in poor performance. If sequencer 120 was performing a time sensitive task, and was paused before the task was completed, the pause would effectively abort the task and require that the complete task be restarted after the pause.
Thus, prior art host adapter 100 used signals PAUSE and PAUSEACK, e.g., hold and grant signals, to arbitrate control of bus CIOBUS (for transferring the use of the bus from one bus master to another bus master). For example, the requesting bus master, host adapter driver 165, activated a hold signal, signal PAUSE, to the current bus master, sequencer 120, and in response, the current bus master completed its current instruction, released bus CIOBUS, and activated a grant signal, set bit PAUSEACK, to the requesting bus master to indicate that sequencer 120 had backed off bus CIOBUS.
In response to the grant signal, the requesting bus master changed its bus signals to the driven state and became a second bus master. When use of bus CIOBUS was completed by the second bus master, the second bus master released bus CIOBUS and inactivated the hold signal, signal PAUSE, indicating to the first bus master that bus CIOBUS was available. The first bus master deactivated the grant signal, changed its bus signals to the driven state, and continued processing a possibly interrupted routine.
When the pause occurred during a routine that involved a timing feature, the routine's timing requirement may not have been met and the result was erratic behavior. If the designer failed to recognize all time critical possibilities prior to completion of the design, software work arounds may not be possible and consequently the circuit may fail to function properly. A method is needed to control when and if an on-chip sequencer is paused to provide the performance needed in multi-tasking host adapters and to assure that all time-critical routines are completed in a normal manner without interruption.